Mentor, A Siemens Business HLS IP Developer - 9593 in Noida, India

HLS IP Developer - 9593


Description

Company: Mentor Graphics

Job Title: HLS IP Developer - 9593

Job Location: India - Noida

Job Category: R&D/Software Engineering

Position Overview:

The IP and Reference Design team at Mentor Graphics and the focus of this team is to design and develop HLS IPs and reference hardware designs in advanced application domains ranging in machine learning, computer vision, image and video processing, wireless baseband and various other domains which have high computations workload and need hardware acceleration. In this role, you will use your software and hardware engineering expertise to help solve complex problems in the above mentioned domains, design and optimize algorithms and convert them into area and power efficient solutions for ASIC/FPGA.

Responsibilities:

• Design, implement and optimize algorithms turning them into low-power custom hardware using Catapult-C High Level Synthesis.

• Develop, test, maintain and improve HLS based designs.

• Develop control and test software for the HLS accelerators.

Job Qualifications:

Minimum qualifications:

• Master's/Bachelor's Degree in Electronics Engineering, with 5 years of relevant industrial experience.

• Strong conceptual understanding of signal/image processing, digital communication, digital logic design, microprocessor and computer architecture.

• Experience in breaking down high-level signal/image processing algorithms and turning them into real-time capable digital architectures with sensitivity towards silicon area and power.

• Good understanding and experience on C/C++ Programming and Experience with high-level synthesis design methodologies and tools (e.g. Catapult, Vivado or Stratus).

Preferred qualifications:

• Experience in fixed point modeling of signal/image processing algorithms in environments like Matlab/Simulink or C++

• Knowledge of Deep Convolutional Neural Network architectures and other traditional building blocks used in computer vision.

• Exposure to FPGA prototyping with understanding of SOC architectures and system level interconnects.