Mentor, A Siemens Business FPGA Hardware Engineer (IP, FPGA design/verification) - 9746 in Wilsonville, Oregon
FPGA Hardware Engineer (IP, FPGA design/verification) - 9746
Work Location US - OR, Wilsonville
Req ID 9746
Job Category R&D/Hardware Engineering
Company: Mentor Graphics
Job Title: FPGA Hardware Engineer (RTL, timing) - 9746
Job Location: USA – OR - Wilsonville
Job Category: R&D/Hardware Engineering
FPGA Hardware Design Engineer, Wilsonville, Oregon
Siemens is a global powerhouse focusing on the areas of electrification, automation and digitalization. One of the world’s largest producers of energy-efficient, resource-saving technologies, Siemens is a leading supplier of systems for power generation and transmission as well as medical diagnosis. In infrastructure and industry solutions the company plays a pioneering role.
Siemens PLM is the world leader in the Electronic Design Automation (EDA) market. Our company offers software and hardware design solutions that enable companies to quickly develop leading-edge electronic products by optimizing their costs.
Mentor Graphics has been acquired by Siemens in 2017. With the widest range of products in the industry, Mentor Graphics is the only company in the EDA market to offer an integrated software solution.
Its subsidiary, based in Wilsonville Oregon, develops proprietary technologies to reduce the time needed to design integrated circuits and systems on a chip (prototyping, validation and debugging). As part of its development, the company wishes to strengthen the R&D team by integrating a FPGA hardware design engineer.
Exciting opportunity in Mentor's FPGA Prototyping R&D team. The Wilsonville team focuses on debug software and hardware infrastructure support for Mentor’s FPGA prototyping software system and hardware platform.
As a contributing engineer, you will participate in the design, specification, implementation, test, and maintenance of FPGA RTL hardware IP for our products.
Specific technical responsibilities include:
* Design, implementation and maintenance of IP blocks in Verilog
* Validation and testing using simulation and VPS hardware boards
* RTL synthesis with timing and physical constraints, capacity and performance goals -Specifically, executing Xilinx Vivado and Intel Quartus flows
* Hardware system performance analysis, debug and tuning
* Software development for low level validation of VPS IPs
* Integration of the VPS IPs in coordination with the software team
*Customer support to ensure smooth deployment of the developed features
The candidate should be a self-motivated team player who is skilled and productive at quality-oriented and performance-oriented hardware engineering.
Since the overall team is present in multiple world-wide sites, the ability to travel occasionally to R&D teams and customer sites is necessary
Experience and Education
* Minimum of BSEE or BSCE, MSEE or MSCE preferred
* 3+ years of relevant work experience preferred
* RTL design with SystemVerilog, Verilog and VHDL
* ASIC and/or FPGA implementation and flows (synthesis, place & route) - specifically executing Xilinx Vivado and/or Intel Quartus flows
* RTL IP, Xilinx Vivado IP, Intel Quartus IP and design reuse
* Standardized interconnect fabric SoC design techniques - AXI4, Avalon, Wishbone or equivalent
* PCIe FPGA to host interfacing
* RTL simulation, verification, debug and timing analysis
* Programming languages Python and C/C++
* Current data structures, XML and JSON
* Linux OS
All qualified applicants will receive consideration for employment without regard to race, sex, sexual orientation, gender expression or identity, color, religion, national origin, disability or protected veteran status.